Certain memory cells, including flash memory cells, include at least one floating gate that is/are programmed and erased through one or more program/erase gates, wordlines, or other conductive element(s). Some memory cells use a common program/erase gate extending over a floating gate to both program and erase the cell. Other memory cells include separate program and erase gates extending over a floating gate. In some implementations, the floating gate is formed by a Poly1 layer, while the program and erase gates (or common program/erase gate) are formed by a Poly2 layer that partially overlaps the underlying Poly1 floating gate in the lateral direction. For some memory cells, the manufacturing process includes a floating gate thermal oxidation process that forms a football-shaped oxide over the Poly 1 floating gate. Each cell may include a source region formed in the substrate, e.g., by a high voltage ion implant (HVII), which diffuses laterally beneath a portion of the floating gate.
Some memory cells, e.g., certain flash memory cells, may experience problems due to scaling. FIG. 1 shows an example memory cell structure 100 to illustrate two of such problems that may exist in certain scaled-down cells. Memory cell structure 100 may comprise a structure of a SuperFlash memory cell from Microchip Technology Inc., having a headquarters at 2355 W. Chandler Blvd., Chandler, Ariz. 85224, or modified versions of such memory cell.
Memory cell structure 100, includes two spaced-apart floating gates 104 formed over a substrate 102, with a “football oxide” 106 formed over each floating gate 106, a word line 108 formed over each floating gate 104, and a common erase gate or “coupling gate” 110 formed between and extending over both floating gates 104, and a source region 112 formed below the common erase gate. In this cell, the source region 112 may be formed before forming the word lines 108 and the coupling gate 110, e.g., by a high-voltage ion implant (HVII) of source dopant (e.g., phosphorus) through an opening in a resist layer formed over the structure, followed by an anneal process to cause a lateral diffusion of the source dopant.
In some configurations or instances, e.g., for particularly small or shrunk cells, the doped source region (e.g., phosphorus doped region) may diffuse an excessive distance laterally underneath the floating gate. Also, in some configurations or instances, during the source implant, portions of each floating gate 104 that are not masked by resist are relatively unprotected, such that a portion of the source dopant (e.g., phosphorus) may penetrate through each football oxide 106 and into each underlying floating gate 104. In particular, dopant received in the upper corners, or “tips” of the floating gate 120 (e.g., the source-side FG erase tips aligned over the source region 112) may result in an undesirable dulling or rounding of the FG tips 120 during subsequent oxidation.
FIG. 2 shows an example flash memory cell structure 200 including two floating gates 204 formed over a substrate 202, each floating gate 204 covered by a flat-topped oxide cap or “stud” region 206, and a conformal nitride layer 230 formed over the structure, e.g., having a thickness of approximately 400 Å. The flat-topped floating gate structures may be formed in any suitable manner, e.g., using the techniques disclosed in co-pending U.S. application Ser. No. 15/921,858 filed Mar. 15, 2018, the entire contents of which application are hereby incorporated by reference.
The conformal nitride layer 230 is intended to act as shield to protect against the HVII source implant dopant from penetrating down into the floating gate poly and causing a dulling or rounding of the floating gate upper corners, or tips 220 during subsequent oxidation. However, in some configurations or instances, the spacing/thickness of the conformal nitride layer 230 may be functionally coupled to the required energy level for the HVII process, as the HVII implant must travel through the nitride layer 230 extending over the substrate 202. The energy level required for an effective HVII process through the nitride layer may result in an undesired amount of lateral diffusion of the source region 212 underneath each floating gate 204.